New Design Techniques for Dynamic Reconfigurable Architectures

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A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs

In recent years, three-dimensional IC (3D IC) has gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation and achievable clock frequencies. However, the reliability of 3D ICs regarding soft errors induced by radiation is not investigated yet. In this work, we propose a method for evaluating the sensitivity of 3D ICs to Single Event Transient induced by Heavy Ions. The flow starts with identifying the characteristics of the generated transient pulses with respect to the radiation profile and 3D layout of the design. Secondly, our method provides a Dynamic Error Rate using a Simulation-based Fault Injection environment. Experimental results achieved applying the approach on a 15nm 3D configurable Look-Up-Table (LUT) designed on two tiers demonstrated the feasibility of the method, showing the vulnerability characterization of four different functional configurations using eight different types of heavy ions

LUMIO, a Lunar Meteoroid Impacts Observer

Accurate models of the distribution of meteoroids in the Earth-Moon system are needed to predict impacts with space equipment and for safe space exploration. The Moon\u27s lack of atmosphere allows for observation of meteoroid impacts: understanding meteoroids is important for studying asteroids, comets, and near-Earth objects. The Lunar Meteoroid Impacts Observer (LUMIO) is a CubeSat mission designed to detect and characterize meteoroid impacts on the far side of the Moon. It can detect small meteoroids too faint for Earth-based observations. LUMIO operates in a Halo orbit at Earth-Moon L2 using the LUMIO-Cam, an optical instrument detecting visible light flashes. The mission is developed under ESA\u27s General Support Technology Program Fly Element. This work highlights the technical challenges and innovative solutions for the LUMIO platform, designed to meet scientific experiment requirements. The satellite will perform a transfer through a Weak Stability Boundary (WSB) trajectory to reach its final orbit. During nominal operations, LUMIO will detect meteoroids for half the lunar month when the Moon is not completely illuminated. The remaining time will be dedicated to station keeping, orbit determination, and optical navigation using an innovative approach. LUMIO features high-reliability technologies to ensure mission success despite mass, volume, power, and cost constraints

EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications

The EuFRATE project aims to research, develop and test radiation-hardening methods for telecommunication payloads deployed for Geostationary-Earth Orbit (GEO) using Commercial-Off-The-Shelf Field Programmable Gate Arrays (FPGAs). This project is conducted by Argotec Group (Italy) with the collaboration of two partners: Politecnico di Torino (Italy) and Technische Universit¨at Dresden (Germany). The idea of the project focuses on high-performance telecommunication algorithms and the design and implementation strategies for connecting an FPGA device into a robust and efficient cluster of multi-FPGA systems. The radiation-hardening techniques currently under development are addressing both device and cluster levels, with redundant datapaths on multiple devices, comparing the results and isolating fatal errors. This paper introduces the current state of the project’s hardware design description, the composition of the FPGA cluster node, the proposed cluster topology, and the radiation hardening techniques. Intermediate stage experimental results of the FPGA communication layer performance and fault detection techniques are presented. Finally, a wide summary of the project’s impact on the scientific community is provided

An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-based FPGAs

Reconfigurable SRAM-based Field Programmable Gate Arrays (FPGAs) are everyday more attractive due to their high integration, performance, flexibility, and upgradability. Run-time reconfiguration improves the reconfigurable computing paradigm allowing to rewrite just a portion of the FPGA configuration memory on-line. This enhances the flexibility and provides opportunities for new high-performing architectures able to adjust in-flight the hardware to the current payload. However, the performance of reconfigurable architectures is bounded by the efficiency of the reconfiguration procedure, which in turn is bounded by the amount of configuration frames to be rewritten in the memory. Furthermore, the lack of tools and design software to implement optimized reconfigurable architectures makes their performance less efficient than expectation. In this work, we propose an approach to enhance the performance of reconfigurable systems by reducing the reconfiguration time of reconfigurable resources. Our method is based on a frame-driven routing algorithm able to drastically reduce the number of configuration memory frames used in the design. We evaluate the optimization achieved with our algorithm on several benchmark circuits of different size and we investigate the performance and the routability for different placement solutions. Experimental results confirm that our approach reduces the reconfiguration time up to 40% with respect to traditional reconfiguration approaches for a wide range of circuits